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[1]         钟祺,王晶,管雪涛,黄涛,王克义。基于数据对象规模的RANK级内存分配方法。计算机研究与发展,50,2013。

[2]         贾宁, 杨春, 佟冬, 王克义。动态翻译系统中的间接转移关联软件预测算法。计算机研究与发展,50,2013。

[3]         黄涛、王晶、管雪涛、钟祺、王克义。采用分区域管理的软硬件协作高能效末级高速缓存设计。计算机辅助设计与图形学学报,25(11),pp:1658-1667,2013。

[4]         Zhang ZH, Wang XY, Tong D et al. Active store window: Enabling far store-load forwarding with scalability and complexity- efficiency. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY (JCST), 27(4), pp: 769–780, 2012.

[5]         谭明星,刘先华,张吉豫,程旭。基于优化回溯模型的无重叠模调度算法。电子学报,40(8),pp:1681-1686,2012。

[6]         Mingxing Tan, Xianhua Liu, Jiyu Zhang, Dong Tong, Xu Cheng. Compiler-Directed Value Correlation for Indirect Branch Prediction. Chinese Journal of Electronics, 21(3), pp: 414-418, 2012.

[7]        Zi-Chao Xie, Dong Tong, Ming-Kai Huang, Qin-Qing Shi, Xu Cheng. SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers. Journal of Computer Science and Technology (JCST), 27(4), pp: 754-768, 2012.

[8]         谭明星,刘先华,张吉豫,佟冬,程旭。一种混合型值关联间接跳转预测机制。电子学报,40(11),pp: 2298 - 2302,2012。

[9]         党向磊,王箫音,佟冬,陆俊林,程旭,王克义。面向按序执行处理器的预执行指导的数据预取方法。电子学报,40(11),pp: 2145-2151,2012

[10]        张吉豫,刘先华,谭明星,程旭,丛京生。一种针对位操作密集应用的扩展指令自动选择方法。电子学报,40(2),pp: 209-214, 2012.

[11]        帖猛,程旭,可校准电源偏差并基于标准单元的温度传感器。北大学报(自然科学版),46(1),pp: 17-22,2011。

[12]        张良,佟冬,程旭,王克义。覆盖矩阵反馈的演化测试程序生成方法。计算机辅助设计与图形学学报,23(3),pp:456-464, 2011年。

[13]        黄侃,佟冬,程旭。基于行冲突预测的内存控制器QoS 管理机制。电子学报,39(2), pp: 358-363,2011。

[14]        庞九凤,佟冬,李皓,何浪,程旭。面向基于x86处理器和AMBA的系统芯片的全系统模拟器PKUsim-86。电子学报,39(2),pp:351-357,2011。

[15]        王箫音,佟冬,党向磊,冯毅,程旭。一种高能效的面向单发射按序处理器的预执行机制。电子学报,39 (2),pp: 458-463,2011。

[16]        钮艳,夏虞斌, 杨春, 程旭。基于受限行为约束策略的桌面计算系统交互性能测量方法。计算机研究与发展,48(2),pp: 338-345,2011。

[17]        Yan Niu, Chun Yang, Yubin Xia, Xu Cheng. Extending Virtual Machine Memory with Hypervisor Exclusive Cache. Acta Scientiarum Naturalium Universitatis Pekinensis,47(2),pp:251-257,2011.

[18]        Yang Zhang, Xue-tao Guan, Xu Cheng. Application-Specific Graphical Caching in Thin-Client Computing. Acta Scientiarum Naturalium Universitatis Pekinensis,47(3),pp:427-434,2011.

[19]        庞九凤,陆俊林,李皓,佟冬,程旭。一种面向Microsoft Windows的AMBA设备PCI虚拟化机制。电子学报,39(5),pp:1013-1019,2011。

[20]        林桦,佟冬,黄侃,王克义,程旭。结合PVT模拟和排队模型的系统级主存性能分析。计算机辅助计与图形学报,12,pp:2228-2236,2011。

[21]        WANG Jing, GUAN Xue-tao, CHENG Xu,Jason Cong. Wireless Network Interface Card Energy Management for Interactive Applications. The Chinese Journal of Electronics, 20(1),pp:45-51,2011.

[22]        陆晓凤,刘锋,佟冬,王克义。一种支持H.264 High Profile的高效可重构反变换VLSI结构。电子学报,38(5),pp: 1072-1076,2011。

[23]        张良,易江芳,佟冬,程旭,王克义。使用局部建模的微处理器测试程序自动生成方法。电子学报,20(7),pp:1639-1644,2011。

[24]        钮艳,郑衍松,杨春,程旭。基于客户操作系统行为的虚拟机内存均衡方法。电子学报,39(9),pp:2178-2183,2011。

[25]        党向磊,王箫音,佟冬,陆俊林,易江芳,王克义。一种基于值预测和指令复用的按序处理器预执行机制。电子学报,39(12),pp:2880-2883,2011。

[26]        李皓,郑衍松,庞九凤,佟 冬,程 旭。EmBIOS:一种支持MS Windows的嵌入式系统BIOS设计。北大学报自然科学版,48(1),pp:20-28,2011。

[27]        刘丹,冯毅,党向磊,佟冬,程旭,王克义。一种降低系统芯片中跨时钟域设计和验证复杂度的方法。通信学报,11,pp:151-158,2012。

[28]        张吉豫,刘先华,谭明星,程旭,丛京生。一种针对位操作密集应用的扩展指令自动选择方法。电子学报,40(2),pp:209-214,2012。

[29]        张吉豫,刘先华,梁堃,程旭。一种基于人工神经网络的基本块重排方法。北京大学学报(自然科学版),47(1),pp:9-16,2011。

[30]        谢子超,陆俊林,佟冬,王箫音,程旭。一种面向超标量处理器的高能效指令缓存路选择技术。电子学报,39(11),pp:2473-2479,2011。

[31]        李皓,李险峰,庞九凤,黄侃,郑衍松,佟冬,程旭。一种基于固件的系统芯片协同验证平台。计算机辅助设计与图形学学报,23(9),pp:1593-1602,2011。

[32]        刘丹,冯毅,佟冬,程旭,王克义。面向内存访问性能优化的总线仲裁方法。计算机研究与发展,5,pp:1061-1071,2012。

[33]        王箫音,佟冬,党向磊,陆俊林,程旭,. 面向按序执行处理器的预执行机制设计空间探索(英文)[J]. 北京大学学报(自然科学版)网络版(预印本),2010,(2).

[34]        张良,佟冬,林桦,程旭,王克义,. 基于多目标演化算法的测试程序生成[J]. 计算机辅助设计与图形学学报,2010,(8).

[35]        黄侃,佟冬,刘洋,杨寿贵,程旭,. MCS-DMA:一种面向SoC内DMA传输的内存控制器优化设计[J]. 电子学报,2010,(3).

[36]        庞九凤,李险峰,谢劲松,佟冬,程旭,. 基于支持向量机的微体系结构设计空间探索(英文)[J]. 北京大学学报(自然科学版),2010,(1).

[37]        聂久焘, 程旭, 王克义. 一种高效的完全值编号算法. 电子学报. 2010 Vol. 38(2): 416-421.

[38]        Xu Cheng, Xiaoyin Wang, Junlin Lu, Jiangfang Yi, Dong Tong, Xuetao Guan, Feng Liu, Xianhua Liu, Chun Yang, Yi Feng. Research Progress of UniCore CPUs and PKUnity SoCs. Journal of Computer Science and Technology

            (JCST), March 2010, Vol.25, No.2, pp.200-213.

[39]        帖猛,程旭,可校准电源偏差并基于标准单元的温度传感器,北大学报自然科学版,46:2010

[40]        夏虞斌, 杨春, 钮艳, 程旭. 基于Xen平台的虚拟机交互式性能隔离改进[J]. 北京大学学报(自然科学版), 2010, (01) :41-47

[41]        Yubin Xia, Chun Yang, Yan Niu, and Xu Cheng. Credit-HC: An I/O-friendly CPU Scheduler for Xen. The Chinese Journal of Electronics (CJE), 2010.

[42]        郑衍松,佟冬,李皓,王克义,程旭,. FaLoFiN:基于不确定性过滤的硬件故障局部化方法[J]. 计算机辅助设计与图形学学报,2010,(7).

[43]        郑衍松,佟冬,王克义,程旭. MDCI:基于多粒度动态控制流不变式的硬件故障局部化.电子学报, 2010, (11).

[44]        谢劲松,佟冬,李险峰,庞九凤,王克义, and 程旭. "RiTLB:基于存储区域重用的iTLB设计," 北京大学学报(自然科学版),  Vol.45, No.04, pp.9-17, 2009.

[45]        聂久焘, and 程旭. "一种收益驱动的语义代码移动算法,"  北京大学学报(自然科学版),  Vol.45, No.04, pp.599-606, 2009.

[46]        冯毅, 许经纬, 易江芳, 佟冬, and 程旭. "面向模型检验的跨时钟域设计电路特性生成方法,"  电子学报,  Vol.37, No.02, pp. 258-265, 2009.

[47]        郑衍松, 佟冬, 李皓, 庞九凤, 王克义, and 程旭.  "MS Windows兼容的系统芯片硬件核心的分析与实践,"  北京大学学报(自然科学版),  Vol. 45, No.06, pp.973-978, 2009.

[48]        陈杰, 李险峰, 佟冬, 王克义, and 程旭. "基于贝叶斯推理和向量压缩技术的最大功耗分析,"  北京大学学报(自然科学版), Vol.45, no.02, pp.215-221, 2009.

[49]        王箫音, 佟冬, 孙含欣, and 程旭. "面向访问需求的数据缓存泄漏功耗管理方法,"  电子学报,  Vol.37, No. 2, pp. 362-366,  2009.

[50]        方昊, 姚博, 宋晓笛, and 程旭. "双游程无关位填充算法,"  电子学报,  Vol. 37, No.1,  pp.1-6, 2009.

[51]        方昊, 宋晓笛, and 程旭. "用扫描链重构来提高EFDR编码的测试压缩率和降低测试功耗," 计算机辅助设计与图形学学报, Vol.21, No.09, pp. 1290-1297, 2009.

[52]        方昊, 宋晓笛,  and 程旭. "CacheCompress:一种新颖的面向IP核的动态字典测试压缩技术,"  北京大学学报(自然科学版), Vol. 45, No. 05, pp.776-782,  2009.

[53]        王逵, 董海瀛, and 程旭. "针对面积优化的时钟偏斜规划算法," 北京大学学报(自然科学版),  Vol.45, No.1, pp. 29-34, 2009.

[54]        Lu Junlin, Liu Dan, Tong Dong. "An Arbitration Approach of Efficient Bandwidth Allocation and Low Latency for SoC Communication," Acta Scientiarum Naturalium Universitatis Pekinensis,,  Vol.45, No.01, pp.20-28, 2009.

[55]        程旭,陆俊林,易江芳,and刘姝, "面向UMPC的北大众志-SK系统芯片设计," 计算机学报,  Vol.31, No.11,  pp. 1877-1887, 2008.

[56]        赵雨来, 佟冬, and 程旭, "利用年龄编码的Bloom过滤算法降低Load-Store队列功耗," 北京大学学报(自然科学版), Vol. 44, No. 4, 2008. .

[57]        Xie Jinsong, Li Xianfeng, Tong Dong, Chen Jie, and X. Cheng, "A Low-Power dTLB Design Based on Memory Region Encoding," The Chinese Journal of Electronics, Vol.17, No,4, 2008.

[58]        Chun Yang, Yan Niu, Yubin Xia, and X. Cheng, "Performance Analysis of Interactive Desktop Applications in Virtual Machine Environment," The Chinese Journal of Electronics, Vol.36, No.2, pp. 242-246, 2008.

[59]        Lin Hua, Zhang Liang, Tong Dong, Li Xianfeng, and X. Cheng. "A Fast Hierarchical Multi-Objective Mapping Approach for Mesh-Based Networks-on-Chip,"  Acta Scientiarum Naturalium Universitatis Pekinensis,  Vol.44,No.9,  pp.711-720, 2008.

[60]        Shu Liu, Xiaogang Gou, Ning Qu, Xianfeng Li, and X. Cheng. "SSDC: A Split Data Cache Design for Sequential Access Intensive Applications," Acta Scientiarum Naturalium Universitatis Pekinensis, Vol. 44, No. 3, pp. 359-369, 2008.

[61]        冯毅, 易江芳, 刘丹, 佟冬, and 程旭, "面向SoC系统芯片中跨时钟域设计的模型检验方法,"  电子学报,  Vol.36, No.5, pp.886-892, 2008.

[62]        赵雨来, 李险峰, 佟冬, and 程旭, "一种基于活跃周期的低端口数低能耗寄存器堆设计," 计算机学报,Vol.31, No.2,  pp.1-10, 2008.

[63]        林桦,李险峰,佟冬, and 程旭, "保证QoS的片上网络低能耗映射与路由方法," 计算机辅助设计与图形学学报,Vol. 20, No.4, pp.425-431, 2008.

[64]        段炼, 许浒, 王逵, and 程旭., "给定偏差约束下的时钟布线局部拓扑构造优化算法," 计算机辅助设计与图形学学报, Vol.20, No.4, 2008.

[65]        陈杰, 佟冬, 李险峰, 谢劲松, and 程旭, "基于切片分析的CMOS组合电路贝叶斯推理动态功耗模型," 半导体学报英文版, Vol.29, No.3, pp.502-509, 2008.

[66]        H. Sun, K. Yang, Y. Zhao, T. Dong, and X. Cheng, "CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs," Journal of Computer Science and Technology, vol. 23, pp. 141-153, 2008.

[67]        赵晓莺, 易江芳, 佟冬, and 程旭, "利用遗传算法实现CMOS组合电路静态功耗优化," 北京大学学报(自然科学版), vol. 43, p. 421~427, 2007.

[68]        赵晓莺, 佟冬, and 程旭, "VSF: CMOS组合电路的静态功耗评估模型," 半导体学报, vol. 28, p. 789~795, 2007.

[69]        易江芳, 佟冬, and 程旭, "使用贝叶斯网络的高效模拟矢量生成方法," 计算机辅助设计与图形学学报, vol. 19, p. 616~621, 2007.

[70]        杨春, 夏虞斌, 钮艳, and 程旭, "一种用于网络计算机系统的半集中计算模型," 北京大学学报(自然科学版), vol. 43, p. 703~708, 2007.

[71]        王宏伟, 陆俊林, 佟冬, and 程旭, "层次化片上网络结构的簇生成算法," 电子学报, vol. 35, p. 916~920, 2007.

[72]        王宏伟, 陆俊林, 佟冬, and 程旭, "层次化的片上网络设计方法," 北京大学学报(自然科学版), vol. 43, p. 669~676, 2007.

[73]        曲宁, 袁鹏, 管雪涛, and 程旭, "网络计算机典型应用程序的d-TLB行为分析," 北京大学学报(自然科学版), vol. 43, p. 85~91, 2007.

[74]        刘先华, 杨阳, 张吉豫, and 程旭, "一种基于子结构分析的基本块重排算法," 软件学报, 2008,(7)..

[75]        刘锋, 代国定, and 庄奕琪, "二维DCT图像处理器的低功耗实现," 电路与系统学报, vol. 12, p. 102~106, 2007.

[76]        段炼, 方昊, 王逵, 帖猛, and 程旭, "一种10ps以下时钟偏差的纯数字电路分频器设计," 电路与系统学报, 2009,(6).

[77]        陈杰, 赵晓莺, 李险峰, 佟冬, and 程旭, "基于三维特征参数的贝叶斯推理电路功耗模型," 计算机辅助设计与图形学学报, vol. 19, pp. 1241-1246, 2007.

[78]        Y. Zhao, X. Li, T. Dong, and X. Cheng, "An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking," Journal of Computer Science and Technology, vol. 22, pp. 15-24, 2007.

[79]        H. Sun, X. Wang, D. Tong, and X. Cheng, "A Low-Leakage Pipelined Instruction Cache Design," Journal of Peking University (Natural Science Series),  vol 44, 2008.

[80]        N. Qu, Y. Zhao, X. Guan, and X. Cheng, "Unichos: A Full System Simulator for Thin Client Platform," Chinese Journal of Electronics, vol. 16, pp. 401-405, 2007.

[81]        S. Liu, X. Guan, and X. Cheng, "DTM:A New Mechanism for Extensible Operating Systems," The Chinese Journal of Electronics, vol. 16, pp. 591-597, 2007.

[82]        X. Li, Y. Liang, T. Mitra, and A. Roychoudhury, "Chronos: A timing analyzer for embedded software," Science of Computer Programming, vol. 69, pp. 56-67, 2007.

[83]        X. Guan, S. Liu, and X. Cheng, "Multiple-Interface Operating Systems Designed for Thin-Client Platforms," The Chinese Journal of Electronics, vol. 16, pp. 227-230, 2007.

[84]        L. Duan, H. Xu, K. Wang, and X. Cheng, "Power-Aware Gated Clock Routing with Merging Cost Backward Annotation Using Simulated Annealing Method," Journal of Peking University (Natural Science Series), vol. 43, pp. 694-702, 2007.

[85]        易江芳, 佟冬, and 程旭, "基于关键信号的路径覆盖率模型," 计算机辅助设计与图形学学报, vol. 18, p. 1085~1091, 2006.

[86]        易江芳, 佟冬, and 程旭, "使用遗传算法自动生成模拟矢量的验证平台," 北京大学学报(自然科学版), vol. 42, p. 668~673, 2006.

[87]        许俊娟 and 程旭, "时间约束调度中功能单元的下限估算," 计算机辅助设计与图形学学报, vol. 18, p. 532~537, 2006.

[88]        许俊娟 and 程旭, "两种不同前提下的多电压调度对比," 计算机辅助设计与图形学学报, vol. 18, p. 545~550, 2006.

[89]        刘强, 佟冬, and 程旭, "部分并行的蒙哥马利模乘法器实现研究," 电子学报, vol. 34, p. 1537~1542, 2006.

[90]        X. Li, A. Roychoudhury, and T. Mitra, "Modeling out-of-order processors for WCET analysis," Real-Time Systems, vol. 34, pp. 195-227, 2006.

[91]        宋传华 and 程旭, "基于北大众志-863 CPU系统芯片的多级TLB性能研究," 电子学报, vol. 33, p. 363~366, 2005.

[92]        刘强, 佟冬, and 程旭, "一款RSA模乘幂运算器的设计与实现," 电子学报, vol. 33, p. 923~927, 2005.

[93]        刘强, 马芳珍, 佟冬, and 程旭, "使用改进的心动阵列结构实现RSA公共密钥算法," 北京大学学报(自然科学版), vol. 41, p. 495~500, 2005.

[94]        刘强, 马芳珍, 佟冬, and 程旭, "一款高吞吐率RSA密码处理器的设计," 北京大学学报(自然科学版), vol. 41, p. 754~763, 2005.

[95]        刘强, 马芳珍, 佟冬, and 程旭, "基于新型脉动阵列的RSA密码处理器," 北京大学学报(自然科学版), vol. 41, p. 495~500, 2005.

[96]        Y. Zhao, H. Sun, J. Xie, X. He, and X. Lin, "Integrated Co-Simulation and Verification for Microprocessor on VCSTM Platform," Synopsys User Group(SNUG), 2005.

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[1]      Qiaoli Xiong, Jiangfang Yi, Tianbao Song, Zichao Xie, Dong Tong. VFCC: A Verification Framework on Cache Coherence Using Parallel Simulation. In Proceedings of the 18th Asia and South Pacific Design Automation Conference(ASP-DAC), pp 705-710, 2013.

[2]      Xianglei Dang, Xiaoyin Wang, Dong Tong, Zichao Xie, Lingda Li, and Keyi Wang. An Adaptive Filtering Mechanism for Energy Efficient Data Prefetching. Asia and South Pacific Design Automation Conference (ASP-DAC), 2013.

[3]      Ning Jia, Chun Yang, Jing Wang, Dong Tong, and Keyi Wang, "SPIRE: improving dynamic binary translation through SPC-indexed indirect branch redirecting", in Proceedings of the 9th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments (VEE) , Houston, Texas, USA pp 1-12, 2013.

[4]      Mingli Xie, Dong Tong, Yi Feng, Kan Huang, Xu Cheng, Page Policy Control with Memory Partitioning for DRAM Performance and Power Efficiency, in International Symposium on Low Power Electronics and Design (ISLPED), pp 298-303, 2013.

[5]      Guan Xuetao, Cheng Xu, A Hybrid-ISA Multicore System for Mobile Computing. The 4th Workshop on SoCs, Heterogeneous Architectures and Workloads, Held in conjunction with HPCA-19. Feb. 2013.

[6]      Tao Huang, Qi Zhong, Xuetao Guan, Xiaoyin Wang, Xu Cheng, Keyi Wang. Reducing Last Level Cache Pollution Through OS-Level Software-Controlled Region-Based Partitioning. The Proceedings of the 27th ACM Symposium on Applied Computing (SAC), pp: 1779-1784, Riva del Garda (Trento), Italy, March 26-31, 2012.

[7]      Qi Zhong,Xuetao Guan, Tao Huang, Xu Cheng, and Keyi Wang. Affinity aware DMA Buffer Management for Reducing Off-chip Memory Access. The Proceedings of the 27th Annual ACM Symposium on Applied Computing (SAC), pp: 1588-1593, Trento, Italy, March 26-31, 2012.

[8]      Zhenhao Zhang, Dong Tong, Xiaoyin Wang, Jiangfang Yi, Keyi Wang. SOLE: Speculative One-cycle Load Execution with Scalability, High-performance and Energy-efficiency. IEEE International Conference on Computer Design (ICCD), Montreal, Canada, 2012.

[9]      Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, and Xu Cheng. Improving inclusive cache performance with two-level eviction priority. In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD), Montreal, Canada, Sep 30-Oct 3, 2012.

[10]     Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, and Xu Cheng. Optimal bypass monitor for high performance last-level caches. In Proceedings of the 21th ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, USA, Sep 19-23, 2012.

[11]     Mingxing Tan, Xianhua Liu, Dong Tong, Xu Cheng. CVP: An Energy-Efficient Indirect Branch Prediction with Compiler-Guided Value Pattern. In Proceedings of the 26th ACM/SIGARCH International Conference on Supercomputing (ICS), pp: 111-120, Venice, Italy, June 25-29, 2012.

[12]     Xianglei Dang, Xiaoyin Wang, Dong Tong, Junlin Lu, Jiangfang Yi, and Keyi Wang. S/DC: A Storage and Energy Efficient Data Prefetcher. In Proceedings of the Design Automation and Test in Europe (DATE), pp: 461-466, Dresden, Germany, 2012.

[13]     Mingxing Tan, Xianhua Liu, Zichao Xie, Dong Tong, Xu Cheng. Energy-Efficient Branch Prediction with Compiler-Guided History Stack. In Proceedings of the Design, Automation and Test in Europe (DATE), pp: 449-454, Dresden, Germany, 2012.

[14]     Yan Niu, Chun Yang, Xu Cheng. Dynamic Memory Demand Estimating based on Guest OS Behaviors for Virtual Machines. The 9th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), pp: 81-86, May 2011.

[15]     Jing Wang, Xuetao Guan, Xu Cheng. Interaction-Aware Dynamic Power Optimization Scheme for Wireless Network Interface Cards. The International Conference on Smart Grid and Home (SGH), pp: 244-249, 2011.

[16]     Liucheng Guo, Jiangfang Yi, Liang Zhang, Xiaoyin Wang, Dong Tong. CGA: Combining Cluster Analysis with Genetic Algorithm for Regression Suite Reduction of microprocessor. IEEE International SoC Conference (SoCC), pp: 207-212, 2011.

[17]     Zichao Xie, Dong Tong, Mingkai Huang, Xiaoyin Wang, Qinqing Shi, Xu Cheng. TAP Prediction: Reuse Conditional Branch predictor Indirect Branches with Target Address Pointers. The International Conference on Computer Design (ICCD), pp: 119-126, 2011.

[18]     Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong, Xu Cheng. FPGA Prototyping of an AMBA-Based Windows-Compatible SoC, Proceedings of the 18th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, 2010. 

[19]     Jiyu Zhang, Zhiru 、Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng and Jason Cong, "Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration", Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, CA, February 2010.

[20]     Shu Liu, Xu Cheng, Xuetao Guan, Dong Tong, and. Energy Efficient Management Scheme for Heterogeneous Secondary Storage System in Mobile Computers. Proceedings of the 25th ACM Symposium on Applied Computing, Sierre, Switzerland, 2010, pp. 251-257.

[21]     Meng Tie, Haiying Dong, Tong Wang and Xu Cheng. “Dual-Vth Leakage Reduction with Fast Clock Skew Scheduling Enhancement,” Design, Automation and Test in Europe Conference and Exhibition, Proceedings, 2010.

[22]     Hao Li,Dong Tong, Kan Huang, Xu Cheng. "FEMU: A Firmware-Based Emulation Framework for SoC Verification", International Conference on Harware/Software Codesign and System Synthesis (CODES+ISSS), Scottsdale, Arizona, USA, Oct. 24-29, 2010.

[23]     Dan Liu, Yi Feng, Jingjin Zhou, D ong Tong, Xu Cheng, Keyi Wang. TERA: A FPGA-Based Trace-Driven Emulation Framework for Designing On-Chip Communication Architectures.IEEE International SoC Conference, Las Vegas, Nevada,USA, September 27-29, 2010.

[24]    Zichao Xie, Dong Tong, Xu Cheng, "WHOLE: A Low Energy I-Cache with Separate Way History", IEEE International Conference on Computer Design(ICCD’09), Lake Tahoe, USA, pp.137-143, 2009.

[25]     Yubin Xia, Chun Yang, Xu Cheng, PaS: A Preemption-aware Scheduling Interface for Improving Interactive Performance in Consolidated Virtual Machine Environment, The Proceedings of the 15th International Conference on Parallel and Distributed Systems (ICPADS'09), Shenzhen, China, pp.340-347, 2009.

[26]     Yang Zhang, Xue-tao Guan, Tao Huang, Xu Cheng. “A Heterogeneous Auto-offloading Framework Based on Web Browser for Resource-Constrained Devices”. in Proceedings of the 4th International Conference on Internet and Web Applications and Services (ICIW), Venice, Italy, 2009.

[27]     Yubin Xia, Yan Niu, Yansong Zheng, Ning Jia, Chun Yang, Xu Cheng. Analy-sis and Enhancement for Interactive-Oriented Virtual Machine Scheduling. In Proceeding of International Workshop on End-User Virtualization (EUV), Shanghai, China, 2008.

[28]     H. Fang, C. Tong, B. Yao, X. Song, and X. Cheng, "CacheCompress: A Novel Approach for Test Data Compression with Cache for IP Embedded Cores," in 2006 International Conference on Computer-Aided Design (ICCAD'07), San Jose, CA, USA, 2007, pp. 509-512.

[29]     X. Li, A. Roychoudhury, T. Mitra, P. Mishra, and X. Cheng, "A Retargetable Software Timing Analyzer Using Architecture Description Language," in 12th Asia and South Pacific Design Automation Conference (ASP-DAC'07), 2007, pp. 396-401.

[30]     H. Sun, Z. Shang, X. Wang, X. Li, D. Tong, and X. Cheng, "LAFI: Look-Ahead Mechanism for Energy-Efficient Branch Prediction," in IEEE Computer Society Annual Symposium on VLSI(ISVLSI), Porto Alegre, Brazil, 2007, p. xxx. to appear.

[31]     H. Fang, C. Tong, and X. Cheng, "RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power," in Proceedings of the 2007 Conference on Asia South Pacific Design Automation, Yokohama, Japan, 2007, pp. 732-737.

[32]     X. Liu, J. Zhang, K. Liang, Y. Yang, and X. Cheng, "Basic-block Reordering Using Neural Networks," in The first Workshop on Statistical and Machine learning approaches applied to ARchitectures and compilaTion (SMART'07), Ghent, Belgium, 2007, pp. 11-25.

[33]     N. Qu, Y. Zhao, X. Guan, and X. Cheng, "Unichos: A Full System Simulator for Thin Client Platform," in Proceeding of the 22nd Annual ACM Symposium on Applied Computing, Seoul, Korea, 2007, pp. 1552-1556.

[34]     X. Liu, J. Zhang, and X. Cheng, "Efficient Code Size Reduction without Performance Loss," in Proceedings of the International Symposium on Applied Computing (SAC) Seoul, Korea, 2007, pp. 666-672.

[35]     X. Liu, J. Zhang, and X. Cheng, "NISD:A Framework for automatic Narrow Instruction Set Design," in The 2007 International Conference on Embedded Systems and Software (ICESS'07), Daegu, Korea, 2007, pp. 271-282.

[36]     C. Yang, Y. Niu, Y. Xia, and X. Cheng, "A Fast Lossless Codec of Continuous-Tone Images for Thin Client Computing," in Proceedings of the 2007 Data Compression Conference (DCC), 2007, p. 409.

[37]     C. Yang, Y. Niu, Y. Xia, and X. Cheng, "A Fast and Efficient Codec for Multimedia Applications in Wireless Thin-Client Computing," in Proceedings of the 8th IEEE Symposium on a World of Wireless, Mobile and Multimedia Networks (WoWMoM), 2007, pp. 1-12.

[38]     Y. Feng, Z. Zhou, D. Tong, and X. Cheng, "Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design," in Design Automation and Test in Europe(DATE'2007), 2007, pp. 1385-1390.

[39]     K. Wang, L. Duan, and X. Cheng, "ExtensiveSlackBalance: an Approach to Make Front-end Tools Aware of Clock Skew Scheduling," in Proceedings of the 43rd Design Automation Conference(DAC'2006), San Francisco, CA, USA, 2006, pp. 951-954.

[40]     S. Shi, F. Liu, and X. Cheng, "A Low Complexity MPEG Video Decoder with Arbitrary Downscaling Capability," in IEEE 4th Workshop on Embedded System for Real-Time Multimedia, 2006, pp. 13-18.

[41]     X. Zhao, J. Yi, D. Tong, and X. Cheng, "Leakage Power Reduction for CMOS Combinational Circuits," in The 8th International Conference on Solid-State and Integrated-Circuit Technology, 2006.

[42]     X. Zhao, K. Wang, D. Tong, and X. Cheng, "A Leakage Power Estimation Method for Standard Cell Based Design," in Proceedings of 2005 IEEE  Conference on Electron Devices and Solid-State Circuits,, 2005.

[43]     N. Qu, X. Gou, and X. Cheng, "Using Uncacheable Memory to Improve Unity Linux Performance," in Workshop on Interaction between Operating System and Computer Architecture, Austin,TX, 2005, pp. 27-32.

[44]     Y. Zhang, S. Liu, W. Jia, and X. Cheng, "BluePower - A New Distributed Multihop Scatternet Formation Protocol for Bluetooth Networks.," in 34th International Conference on Parallel Processing (ICPP'2005), Oslo, Norway, 2005, pp. 287-294.

[45]     J. Xu, J. Cong, and X. Cheng, "Lower-bound estimation for multi-bitwidth scheduling," in IEEE International Symposium on Circuits and Systems(ISCAS'2005), Kobe, Japan, 2005, pp. 696-699.

[46]     Q. Liu, D. Tong, and X. Cheng, "Non-interleaving architecture for hardware implementation of modular multiplication," in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS'2005), Kobe, Japan, 2005, pp. 660-663.

[47]     D. Chen, J. Cong, and J. Xu, "Optimal Module and Voltage Assignment for Low-Power," in Proceedings of the Asia South Pacific Design Automation Conference, Shanghai, China 2005, pp. 850-855.

[48]     J. Cong, Y. Fan, G. Han, Y. Lin, J. Xu, Z. Zhang, and X. Cheng, "Bitwidth-aware scheduling and binding in high-level synthesis," in Proceedings of the 2005 Conference on Asia South Pacific Design Automation(ASP-DAC'2005), Shanghai, China, 2005, pp. 856-861.

[49]     Z. Dexin, "PURECC: the Compiler Infrastructure for UNICORE architecture," in International Center on System-on-a-chip Workshop, 2002.

[50]     Q. Liu, D. Tong, and X. Cheng, "A New Systolic Architecture without Global Broadcast," in Proceedings of IEEE 7th International Conference on Signal Processing (ICSP'04), Beijing, China, 2004, pp. 527-530.

[51]     Q. Liu, F. Ma, D. Tong, and X. Cheng, "A Regular Parallel RSA Processor," in Proceedings of IEEE 47th International Midwest Symposium on Circuits and Systems (MWSCAS2004), Hiroshima, Japan, 2004, pp. 467-470.

[52]     Q. Liu, F. Ma, D. Tong, and X. Cheng, "Efficient Implementation of the RSA Crypto Processor in Deep Sub-micron Technology," in Proceedings of ICISA 2nd International Conference on Applied Cryptography and Network Security (ACNS'2004), Yellow Mountain, China, 2004, pp. 106-114.

[53]     刘强, 马芳珍, 佟冬, and 程旭, "高性能RSA密码处理器的设计与实现," in 中国电子学会第十届青年学术年会, 2004, p. 429~432.

[54]     Y. Zhao, X. Li, D. Tong, and X. Cheng, "Reuse Distance Based Cache Leakage Control," in 14th IEEE International Conference on High Performance Computing(HiPC'07), 2007, pp. 356-367.

[55]     K. Wang, H. Fang, H. Xu, and X. Cheng, "A Fast Incremented Clock Skew Scheduling Algorithm for Slack Optimization," in 13th Asia and South Pacific Design Automation Conference(ASP-DAC'08), 2008, p. xxx. to appear.